Traditional CMOS (complementary metal oxide semiconductor) techniques include process flows for constructing planar transistors. With planar transistors, transistor density can be increased by decreasing the pitch between transistor gate elements. However, with planar transistors, the ability to decrease gate pitch is limited by the required gate length and spacer thickness. In recent years, there has been significant research and development with regard to vertical transistor structures, which decouple the gate length from the gate pitch requirement and enable scaling of transistor density. In general, vertical transistors are designed to have gate structures that are disposed on multiple sides of a vertical semiconductor fin structure or vertical nanowire. With vertical transistors, device scaling is determined by how closely conductive via contacts to source and drain regions can be placed. Unlike planar transistors, however, where self-aligned contact processes (which determine the spacing between source/drain contacts and a gate electrode) can be used, there are no known techniques for forming self-aligned source/drain contacts for vertical transistors.